The field of single-chip, large scale integration (LSI) microprocessors is advancing at an incredible rate. Progress in the underlying semiconductor technology, MOS, is driving the advance. Every two years, circuit densities are improving by a factor of two, circuit speeds are increasing by a factor of two, and at the same time speed-power products are decreasing by a factor of four. Finally, yield enhancement techniques are driving down production costs and hence product prices, thereby increasing demand and opening up new applications and markets.
One effect of this progress in semiconductor technology is advancement in LSI microprocessors. The latest generation, currently being introduced by several companies is an order of magnitude more powerful than the previous generation, the 8-bit microprocessors of three or four years ago. The new microprocessors have 16-bit data paths and arithmetic capability, and they directly address multiple-megabyte memories. In terms of functional capability and speed, they will outperform all but the high end models of current 16-bit minicomputers.
LSI microprocessor design is now at the stage where better implementation techniques are required in order to control complexity and meet tight design schedules. One technique for achieving these goals is to use microprogramming for controlling the processor. Most of the traditionally claimed benefits of microprogramming, for example, regularity (to decrease complexity), flexibility (to ease design changes), and reduced design costs, apply to the implementation problems for current LSI microprocessor design. Among the constraints which LSI technology imposes on processor implementation are circuit size, circuit speed, interconnection complexity, and package pin count.
There is a fairly constant limit on the size of LSI integrated circuit chips which can be economically produced. Although circuit densities tend to improve over time, the number of gates which can be put on a chip is limited at any given time. Thus a major constraint is to design a data processor which may be implemented within the fixed maximum number of gates.
Another constraint in the implementation of LSI data processors is circuit speed, which is limited primarily by the powder dissipation limits of the semiconductor package in which the LSI circuit is mounted. The large speed gap between emitter-coupled (ECL) and core memory associated with large computer systems is not applicable to microprocessor applications, where often the processor technology and the main memory technology are the same.
With regard to interconnection complexity, internal interconnections on an LSI circuit often require as much chip area as do the logic gates which they connect. Furthermore, LSI circuit layout considerations often restrict the ability to route a signal generated in one section of the chip to another section of the chip. In some instances, it is more practical to duplicate functions on various sections of the chip rather than to provide connection to a single centralized function. Another consideration with regard to LSI circuit technology is that regular structures, such as ROM arrays, can be packed much more tightly than random logic.
Semiconductor packaging technology is also a constraint in that it places limits on the number of pin connections which an LSI chip may have to interface to the outside world. The pin-out limitations can be overcome by time multiplexing pin use, but the resulting slowdown in circuit performance is usually not acceptable.
Finally, customer demand and intense competition among semiconductor manufacturers often dictate that LSI data processors be designed according to tight time schedules. A control structure which reduces the design time for LSI data processors will be greatly appreciated by those skilled in the art. Furthermore, LSI data processors are often designed initially to be enhanced with new instructions in future versions of the data processor. Alternatively, some LSI data processors may be designed with enough flexibility so as to allow particular users to specify a set of instructions adapted to their needs. It will be appreciated by those skilled in the art that a control structure which simplifies modifications of and additions to a basic instruction set for a data processor is a significant improvement over the prior art.
The size of a microprogram control store is related to the number of control words and the number of bits in each control word. Control words having a large number of bits can control actions in the data processor fairly directly. However, a reduction in the overall size of the control store allows for a reduction in the size of the semiconductor chip which implements the data processor. Savings in chip area result in lower semiconductor chip costs since a greater number of such semiconductor chips can be formed from a processed semiconductor wafer. Thus, a data processor adapted to utilize a control store which need not duplicate unique control words containing a large number of bits is likely to reduce the overall size of the control store and lower chip costs.